AS1541 查看數據表（PDF） - austriamicrosystems AG
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AS1541 Datasheet PDF : 20 Pages
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AS1539/AS1541
Data Sheet - Application Information
9 Application Information
Initiating a Conversion
After the AS1539/AS1541 has been write-addressed by the bus master, the A/D converter circuitry is powered on, and
conversions will begin when a command byte bit C0 (see Command Byte on page 12) is received. If the address byte
is valid, the AS1539/AS1541 will return an ACK.
Reading Data
Data can be read from the AS1539/AS1541 by read-addressing the device (LSB of address byte set to 1 (see Com-
mand Byte on page 12)) and receiving the transmitted bytes. Converted data can only be read from the AS1539/
AS1541 once a conversion has been initiated as described in Initiating a Conversion.
Each 12-bit data word (see Figure 27) is returned in two bytes, where D9 is the MSB of the data word, and D0 is the
LSB. Byte 0 is sent first, followed by Byte 1.
Figure 27. Data Word
MSB
6
5
4
3
2
1
LSB
Byte 0
0
0
0
0
D9
D8
D7
D6
Byte 1 D5
D4
D3
D2
D1
D0
0
0
Figure 28 illustrates the interaction between the master and the slave AS1539/AS1541.
The most efficient way to perform continuous conversions is to issue repeated STARTs to the AS1539/AS1541 (to
secure the bus for subsequent ADC conversions) after reading each conversion. It is recommended that during the
conversion mode no data is clocked into the ADC to prevent internal noise. Therefore, after the repeated start com-
mend it is recommanded not to clock in or out any data from the converter for 3.7µs. The ADC powers up after the PD0
bit is clocked in and it takes 1.4µs to fully power up. At a clock frequency of 3.4MHz this time is automatically achieved
and no extra delay should be included.
Figure 28. Read Sequence
ADC Powerdown Mode
ADC Sampling Mode
S 1 0 0 1 0 A1 A0 W A SD C2 C1 C0 PD1 PD0 X X A
Write-Addressing Byte
ADC Conversion Mode
Command Byte
ADC Powerdown Mode *
Sr
1 0 0 1 0 A1 A0 R A 0 0 0 0 D9 D8 D7 D6 A D5 D4 ... D0 0 0 N P
3.7µs
Read-Addressing Byte
From Master to Slave
From Slave to Master
* Dependant on powerdown selection bits PD0 and PD1
Use repeated STARTs to secure the
bus operation and loop back to the
stage of write-addressing for the
next conversion.
Where:
A: Acknowledge (SDA Low)
N: Not Acknowledge (SDA High)
S: START Condition
P: STOP Condition
Sr: Repeated START Condition
W: 0 (Write)
R: 1 (Read)
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Revision 1.02
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