ADMC326 查看數據表（PDF） - Analog Devices
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ADMC326 Datasheet PDF : 31 Pages
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ADMC326
GENERAL DESCRIPTION
The ADMC326 is a low cost, single-chip DSP-based controller,
suitable for permanent magnet synchronous motors, AC induction
motors and brushless dc motors. The ADMC326 integrates a
20 MIPS, fixed-point DSP core with a complete set of motor
control and system peripherals that permits fast, efficient
development of motor controllers.
The DSP core of the ADMC326 is the ADSP-2171, which is
completely code compatible with the ADSP-21xx DSP family
and combines three computational units, data address generators
and a program sequencer. The computational units comprise an
ALU, a multiplier/accumulator (MAC) and a barrel shifter. The
ADSP-2171 adds new instructions for bit manipulation, multipli-
cation (× squared), biased rounding and global interrupt masking.
The system peripherals are the power-on reset circuit (POR),
the watchdog timer and a synchronous serial port. The serial
port is configurable and double buffered, with hardware support
for UART and SCI port emulation.
The ADMC326 provides 512 × 24-bit program memory RAM,
4K × 24-bit program memory ROM and 512 × 16-bit data
memory RAM. The program memory ROM contains the user-
specified program code and is defined using a single metal layer
mask. The program and data memory RAM can be used for
dynamic data storage.
The motor control peripherals of the ADMC326 comprise a
12-bit analog data acquisition system with six analog input
channels and an internal voltage reference. In addition, a three-
phase, 16-bit, center-based PWM generation unit can be used to
produce high accuracy PWM signals with minimal processor
overhead. The ADMC326 also contains two auxiliary PWM
outputs, and nine lines of digital I/O.
Because the ADMC326 has a limited number of pins, a number
of functions such as the auxiliary PWM and the serial commu-
nication port are multiplexed with the nine programmable input/
output (PIO) pins. The pin functions can be independently
selected to allow maximum flexibility for different applications.
DATA
ADDRESS
GENERATOR
#1
DATA
ADDRESS
GENERATOR
#2
INSTRUCTION
REGISTER
PROGRAM
SEQUENCER
14
14
24
BUS
EXCHANGE
16
PM ROM
4K ؋ 24
PM RAM
512 ؋ 24
DM RAM
512 ؋ 16
PMA BUS
DMA BUS
PMD BUS
DMD BUS
INPUT REGS
ALU
OUTPUT REGS
INPUT REGS
MAC
OUTPUT REGS
16
R BUS
INPUT REGS
SHIFTER
OUTPUT REGS
CONTROL
LOGIC
COMPANDING
CIRCUITRY
Figure 3. DSP Core Block Diagram
TIMER
TRANSMIT REG
RECEIVE REG
SERIAL
PORT
6
REV. A
–7–
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