
PRELIMINARY
SWITCHING WAVEFORMS (continued)
CLK
TXD+
1
0
10
1
11
0
1
0 ETD
tTXETD
tTXETD
TXD–
Figure 23. TP Ports Output Timing Diagram
2065200B6-5208A-29
tPWLP
tPERLP
Figure 24. TP Idle Link Test Pulse
VTSQ+
RXD+/–
VTSQ–
tPWKRD
tPWKRD
Figure 25. TP Receive Timing Diagram
tPWKRD
VTHS+
VTHS–
40
Am79C984A