
PRELIMINARY
SWITCHING WAVEFORMS (continued)
SCLK
tSCLK
tSCLKR
tSCLKH
tSCLKL
SI
tSODLY
SO
tSISET
tSIHLD
Figure 15. Control Port Timing
tSCLKF
20265006B5-02A0 -21
CLK
RST
TCLK
tRSTHLD
tRST
or tPRST
Note: TCLK represents internal eIMR timing
tRSTSET
Figure 16. Reset Timing
20650B-21
20650A-22
AMODE, SELI_0
tXRS
tXRH
RST
Figure 17. Mode Initialization
20650B-22
Am79C984A
37