ADT7318ARQZ-REEL71 查看數據表（PDF） - Analog Devices

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ADT7318ARQZ-REEL71

±0.5°C Accurate Digital Temperature Sensor and Quad Voltage Output 12-/10-/8-Bit DACs

Analog Devices 

ADT7316/ADT7317/ADT7318

Write Operation

Figure 54 and Figure 55 show the timing diagrams for a write

operation to the ADT7316/ADT7317/ADT7318. Data is clocked

into the registers on the rising edge of SCLK. When the CS line

is high, the DIN and DOUT lines are in three-state mode. Only

when the CS goes from a high to a low does the part accept any

data on the DIN line. In SPI mode, the address pointer register

is capable of an auto-increment to the next register in the register

map without having to load the address pointer register each

time. In Figure 54, the register address section provides the first

register address that is written to. Subsequent data bytes are

written into sequential writable registers. Therefore, after each

data byte has been written into a register, the address pointer

register auto-increments its value to the next available register.

The address pointer register auto-increments from Address

0x00 to Address 0x3F and loops back to start all over again at

Address 0x00 when it reaches Address 0x3F.

1

9

1

9

SCL

SDA

1

START BY

MASTER

0

0

1 A2 A1 A0 R/W

D7 D6 D5 D4 D3 D2 D1 D0

ACKNOWLEDGE BY

ADT7316/ADT7317/ADT7318

NO ACKNOWLEDGE BY STOP BY

MASTER MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

SINGLE DATA BYTE FROM ADT7316/ADT7317/ADT7318

Figure 53. I2C — Reading a Single Byte of Data From a Selected Register

CS

1

8

1

8

SCLK

DIN

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

START

WRITE COMMAND

REGISTER ADDRESS

CS (CONTINUED)

1

8

SCLK (CONTINUED)

DIN (CONTINUED)

D7 D6 D5 D4 D3 D2 D1

D0

STOP

DATA BYTE

Figure 54. SPI—Writing to the Address Pointer Register Followed by a Single Byte of Data to the Selected Register

CS

1

8

1

8

SCLK

DIN

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

START

WRITE COMMAND

REGISTER ADDRESS

STOP

Figure 55. SPI—Writing to the Address Pointer Register to Select a Register for a Subsequent Read Operation

Rev. B | Page 38 of 44

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