ADSP-21469KBZ-ENG2 查看數據表（PDF） - Analog Devices

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ADSP-21469KBZ-ENG2

SHARC Processor

Analog Devices 

Preliminary Technical Data

ADSP-21469/ADSP-21469W

DATA MODES

The address and data pins of the external memory interface are

muxed (using bits in the SYSCTL register) to support the exter-

nal memory interface data (input/output), the PDAP (input

only), and the FLAGS (input/output). Table 7 provides the pin

settings.

Table 7. Function of Data Pins

DATA PIN MODE

000

001

010

011

100

101

110

111

AMI_ADDR [23:8]

AMI_ADDR [7:0]

AMI_ADDR [23:0]

Reserved

Reserved

FLAGS/PWM [15–0]

Reserved

PDAP (DATA + CTRL)

Reserved

Three-state all pins

AMI_DATA [7:0]

AMI_DATA [7:0]

FLAGS [15–0]

FLAGS [7–0]

BOOT MODES

Table 8. Boot Mode Selection

BOOTCFG2–0

000

001

010

011

100

101

110

111

Booting Mode

SPI Slave Boot

SPI Master Boot

AMI user boot (for 8-bit Flash boot)

Reserved

Link Port 0 Boot

Reserved

Reserved

Reserved

CORE INSTRUCTION RATE TO CLKIN RATIO MODES

For details on processor timing, see Timing Specifications and

Figure 3 on Page 19.

Table 9. Core Instruction Rate/ CLKIN Ratio Selection

CLKCFG1–0

00

01

11

10

Core to CLKIN Ratio

6:1

32:1

Reserved

16:1

Rev. PrB | Page 15 of 56 | November 2008

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