ADSP-21469KBCZ-4(Rev0) 查看數據表（PDF） - Analog Devices

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ADSP-21469KBCZ-4
(Rev.:Rev0)

SHARC Processor

Analog Devices 

ADSP-21469

PMCTL

(LCLKR)

PMCTL

(PLLBP)

CLKIN

XTAL

BUF

PLLI

CLKIN CLK

DIVIDER fINPUT

PMCTL

(INDIV)

PLL

LOOP

FILTER

VCO

PLL

MULTIPLIER

CLK_CFGx/PMCTL (2xPLLM)

PLL

DIVIDER

PMCTL

(PLLD)

fCCLK

PMCTL

(PLLBP)

LINK PORT

CLOCK

DIVIDER

PMCTL

(DDR2CKR)

DDR2

DIVIDER

CCLK

LCLK

CLK_CFGx/

PMCTL

DDR2_CLK

DIVIDE PCLK

BY 2

RESET

DELAY OF

4096 CLKIN

CYCLES

CLKOUT (TEST ONLY)

RESETOUT

BUF

RESETOUT

CORERST

Figure 5. Core Clock and System Clock Relationship to CLKIN

PCLK

CCLK

Rev. 0 | Page 22 of 72 | June 2010

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