ADSP-21261(Rev0) 查看數據表（PDF） - Analog Devices

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ADSP-21261
(Rev.:Rev0)

SHARC® Embedded Processor

Analog Devices 

ADSP-21261

Table 2. Pin Function Descriptions (Continued)

State During and

Pin

Type

After Reset

Function

CLKIN

XTAL

I

Input only

Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21261 clock input.

It configures the ADSP-21261 to use either its internal clock generator or an external

clock source. Connecting the necessary components to CLKIN and XTAL enables the

internal clock generator. Connecting the external clock to CLKIN while leaving XTAL

unconnected configures the ADSP-21261 to use the external clock source such as

an external clock oscillator. The core is clocked either by the PLL output or this clock

input depending on the CLKCFG1–0 pin settings. CLKIN may not be halted,

changed, or operated below the specified frequency.

O

Output only2

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external

crystal.

CLKCFG1–0

I

Input only

Core/CLKIN Ratio Control. These pins set the start-up clock frequency. See Table 5

for a description of the clock configuration modes.

Note that the operating frequency can be changed by programming the PLL multi-

plier and divider in the PMCTL register at any time after the core comes out of reset.

RSTOUT/CLKOUT O

Output only

Reset Out/Local Clock Out. Drives out the core reset signal to an external device.

CLKOUT can also be configured as a reset out pin (RSTOUT). The functionality can

be switched between the PLL output clock and reset out by setting Bit 12 of the

PMCTL register. The default is reset out.

RESET

TCK

I/A

Input only

Processor Reset. Resets the ADSP-21261 to a known state. Upon deassertion, there

is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins

program execution from the hardware reset vector address. The RESET input must

be asserted (low) at power-up.

I

Input only3

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted

(pulsed low) after power-up or held low for proper operation of the ADSP-21261.

TMS

I/S

Three-state with Test Mode Select (JTAG). Used to control the test state machine. TMS has a

pull-up enabled 22.5 kΩ internal pull-up resistor.

TDI

I/S

Three-state with Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a

pull-up enabled 22.5 kΩ internal pull-up resistor.

TDO

O

Three-state4

Test Data Output (JTAG). Serial scan output of the boundary scan path.

TRST

I/A

Three-state with Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed

pull-up enabled low) after power-up or held low for proper operation of the ADSP-21261. TRST has

a 22.5 kΩ internal pull-up resistor.

EMU

O (O/D)

Three-state with Emulation Status. Must be connected to the Analog Devices DSP Tools product

pull-up enabled line of JTAG emulators target board connector only. EMU has a 22.5 kΩ internal pull-

up resistor.

VDDINT

P

Core Power Supply. Nominally +1.2 V dc and supplies the DSP’s core processor

(13 pins on the BGA package, 32 pins on the LQFP package).

VDDEXT

P

I/O Power Supply. Nominally +3.3 V dc (6 pins on the BGA package, 10 pins on the

LQFP package).

AVDD

P

Analog Power Supply. Nominally +1.2 V dc and supplies the DSP’s internal PLL

(clock generator). This pin has the same specifications as VDDINT, except that added

filtering circuitry is required. For more information, see Power Supplies on Page 8.

AVSS

G

GND

G

Analog Power Supply Return.

Power Supply Return. (54 pins on the BGA package, 39 pins on the LQFP package).

1 RD, WR, and ALE are continuously driven by the DSP and will not be three-stated.

2 Output only is a three-state driver with its output path always enabled.

3 Input only is a three-state driver, with both output path and pull-up disabled.

4 Three-state is a three-state driver, with pull-up disabled.

Rev. 0 | Page 13 of 44 | March 2006

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