ADP3182JRQZ-RL 查看數據表（PDF） - Analog Devices
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ADP3182JRQZ-RL Datasheet PDF : 20 Pages
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ADP3182
gain of the amplifier is programmable by adjusting the feedback
resistor. The current information is then given as the difference
of CSREF − CSCOMP. This difference in signal is used as a
differential input for the current limit comparator.
To provide the best accuracy for sensing current, the CSA is
designed to have a low offset input voltage. In addition, the
sensing gain is determined by external resistors so that the gain
can be made extremely accurate.
CURRENT CONTROL MODE AND
THERMAL BALANCE
The ADP3182 has individual inputs for each phase that are used
for monitoring the current in each phase. This information is
combined with an internal ramp to create a current balancing
feedback system, which has been optimized for initial current
balance accuracy and dynamic thermal balancing during
operation. This current balance information is independent of
the average output current information used for the current
limit described previously.
The magnitude of the internal ramp can be set to optimize the
transient response of the system. It also monitors the supply
voltage for feed-forward control to compensate for changes in
the supply voltage. A resistor connected from the power input
voltage to the RAMPADJ pin determines the slope of the
internal PWM ramp. External resistors can be placed in series
with individual phases to create, if desired, an intentional
current imbalance such as when one phase may have better
cooling and can support higher currents. Resistors RSW1 through
RSW3 (see the typical application circuit in Figure 9) can be used
for adjusting thermal balance. Add placeholders for these
resistors during the initial layout so that adjustments can be made
after completing thermal characterization of the design.
To increase the current in any given phase, increase RSW for that
phase (set RSW = 0 for the hottest phase and do not change it
during balancing). Increasing RSW to only 500 Ω substantially
increases the phase current. Increase each RSW value by small
amounts to achieve balance, starting with the coolest phase.
VOLTAGE CONTROL MODE
A high gain-bandwidth voltage mode error amplifier is used for
the voltage-mode control loop. The control input voltage to the
positive input is derived from the internal 800 mV reference.
The output of the amplifier is the COMP pin, which sets the
termination voltage for the internal PWM ramps.
The negative input (FB) is tied to the center point of a resistor
divider from the output sense location. The main loop
compensation is incorporated into the feedback network
between FB and COMP.
SOFT START
The power-on, ramp-up time of the output voltage is set with a
capacitor and resistor in parallel from the DELAY pin to ground.
The RC time constant also determines the current limit latch-
off time as explained in the following section. In UVLO or
when EN is logic low, the DELAY pin is held at ground. After
the UVLO threshold is reached and EN is logic high, the
DELAY capacitor is charged with an internal 20 µA current
source. The output voltage follows the ramping voltage on the
DELAY pin, limiting the inrush. The soft start time depends on
the value of CDLY, with a secondary effect from RDLY.
If either EN is taken low or VCC drops below UVLO, the
DELAY capacitor is reset to ground to prepare for another soft
start cycle. Figure 6 shows a typical soft start sequence for the
ADP3182.
Figure 6. Typical Start-Up Waveforms
Channel 1: CSREF, Channel 2: DELAY,
Channel 3: PWRGD, Channel 4: COMP
CURRENT LIMIT, SHORT-CIRCUIT, AND
LATCH-OFF PROTECTION
The ADP3182 compares a programmable current limit setpoint
to the voltage from the output of the current sense amplifier.
The level of current limit is set with the resistor from the ILIMIT
pin to ground. During normal operation, the voltage on ILIMIT
is 3 V. The current through the external resistor is internally
scaled to produce a current limit threshold of 10.4 mV/µA. If
the difference in voltage between CSREF and CSCOMP rises
above the current limit threshold, the internal current limit
amplifier controls the internal COMP voltage to maintain the
average output current at the limit.
Rev. 0 | Page 10 of 20
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