ADP1706ACPZ-1.3-R7(RevA) 查看數據表（PDF） - Analog Devices

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ADP1706ACPZ-1.3-R7
(Rev.:RevA)

1 A, Low Dropout, CMOS Linear Regulator

Analog Devices 

ADP1706/ADP1707/ADP1708

Data Sheet

Parameter

OUTPUT NOISE

POWER SUPPLY REJECTION RATIO

Symbol

OUTNOISE

PSRR

Test Conditions/Comments

10 Hz to 100 kHz, VOUT = 0.75 V

10 Hz to 100 kHz, VOUT = 3.3 V

1 kHz, VOUT = 0.75 V

1 kHz, VOUT = 3.3 V

Min Typ Max Unit

125

µV rms

450

µV rms

70

dB

56

dB

1 Accuracy when OUT is connected directly to ADJ. When OUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances

of resistors used.

2 Based on an end-point calculation using 10 mA and 1 A loads. See Figure 11 for typical load regulation performance for loads less than 10 mA.

3 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output

voltages above 2.5 V.

4 Start-up time is defined as the time between the rising edge of EN to OUT being at 95% of its nominal value.

5 Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V.

Rev. A | Page 4 of 20

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