ADN2850BCPZ250-RL7 查看數據表（PDF） - Analog Devices
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ADN2850BCPZ250-RL7 Datasheet PDF : 28 Pages
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ADN2850
Timing Diagrams
CS
CPHA = 1
t2
CLK
CPOL = 1
HIGH
SDI OR LOW
t8
SDO
B24*
t1
t5
B23
t4
B23 (MSB)
t7
t6
t10
B23 (MSB)
Data Sheet
t3
B0
t12
t13
t17
B0 (LSB)
t11
t9
B0 (LSB)
HIGH
OR LOW
t14
RDY
t15
t16
*THE EXTRA BIT THAT IS NOT DEFINED IS NORMALLY THE LSB OF THE CHARACTER PREVIOUSLY TRANSMITTED.
THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 2. CPHA = 1 Timing Diagram
CS
CLK
CPOL = 0
HIGH
OR LOW
SDI
t1
t2
B23
t5
t4
t7
t6
B23 (MSB IN)
t8
t10
CPHA = 0
SDO
B23 (MSB OUT)
t3
B0
t12
t13
t17
B0 (LSB)
t11
B0 (LSB)
HIGH
OR LOW
t9
*
t14
RDY
*THE EXTRA BIT THAT IS NOT DEFINED IS NORMALLY THE MSB OF THE CHARACTER JUST RECEIVED.
THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 3. CPHA = 0 Timing Diagram
t15
t16
Rev. E | Page 6 of 28
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