EVAL-ADN2818EBZ 查看數據表（PDF） - Analog Devices

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EVAL-ADN2818EBZ

Continuous Rate 10 Mbps to 2.7 Gbps Clock and Data Recovery ICs

Analog Devices 

Data Sheet

CLK Holdover Mode

This mode of operation is available in LTD mode. In CLK

holdover mode, the output clock frequency remains within

±5% if the input data is removed or changed. To operate in

this mode, the user writes to the I2C to put the part into CLK

holdover mode by setting SEL_MODE[1] = 1. The user must

then initiate a frequency acquisition by writing a 1-to-0 transi-

tion into CTRLB[5], at which time the device locks onto the

input data rate. At this point, the output frequency remains

within ±5% of the initial acquired value regardless of whether

the input data is removed or the data rate changes.

It is important to note that all frequency acquisitions in this

mode must be initiated by writing a 1-to-0 transition into

CTRLB[5]. In this mode, the device does not automatically

initiate a new frequency acquisition when the input is momen-

tarily interrupted or if the input data rate changes.

ADN2817/ADN2818

CDR Bypass Mode

The CDR on the ADN2817/ADN2818 can be bypassed by setting

Bit CTRLD[7] = 1. In this mode, the ADN2817/ADN2818 feed

the input directly through the input amplifiers to the output

buffer, completely bypassing the CDR.

Disable Output Buffers

The ADN2817/ADN2818 provide the option of disabling the

output buffers for power savings. The clock output buffers

can be disabled by setting Bit CTRLD[5] = 1. This reduces

the total power consumption of the device by ~100 mW. For

an additional 100 mW power savings, such as in low power

standby mode, the data output buffers can also be disabled by

setting Bit CTRLD[6] = 1.

Rev. E | Page 29 of 40

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