ADM1065ACPZ 查看數據表（PDF） - Analog Devices

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ADM1065ACPZ

Super Sequencer and Monitor

Analog Devices 

Data Sheet

ADM1065

SEQUENCING ENGINE APPLICATION EXAMPLE

The application in this section demonstrates the operation of

the SE. Figure 22 shows how the simple building block of a

single SE state can be used to build a power-up sequence for a

three-supply system. Table 8 lists the PDO outputs for each state

in the same SE implementation. In this system, a good 5 V supply

on VP1 and the VX1 pin held low are the triggers required to

start a power-up sequence. The sequence next turns on the 3.3 V

supply, then the 2.5 V supply (assuming successful turn-on of

the 3.3 V supply). When all three supplies have turned on correctly,

the PWRGD state is entered, where the SE remains until a fault

occurs on one of the three supplies or until it is instructed to go

through a power-down sequence by VX1 going high.

Faults are dealt with throughout the power-up sequence on a case-

by-case basis. The following three sections (the Sequence Detector

section, the Monitoring Fault Detector section, and the Timeout

Detector section) describe the individual blocks and use the

sample application shown in Figure 22 to demonstrate the

actions of the state machine.

Sequence Detector

The sequence detector block is used to detect when a step in

a sequence has been completed. It looks for one of the SE inputs

to change state, and is most often used as the gate for successful

progress through a power-up or power-down sequence. A timer

block that is included in this detector can insert delays into a

power-up or power-down sequence, if required. Timer delays

can be set from 10 μs to 400 ms. Figure 21 is a block diagram of

the sequence detector.

VP1

SUPPLY FAULT

DETECTION

SEQUENCE

DETECTOR

VX5

LOGIC INPUT CHANGE

OR FAULT DETECTION

TIMER

WARNINGS

FORCE FLOW

(UNCONDITIONAL JUMP)

INVERT

SELECT

Figure 21. Sequence Detector Block Diagram

Table 8. PDO Outputs for Each State

PDO Outputs

IDLE1 IDLE2

PDO1 = 3V3ON

0

0

PDO2 = 2V5ON

0

0

PDO3 = FAULT

0

0

EN3V3

1

0

0

EN2V5

1

1

0

If a timer delay is specified, the input to the sequence detector

must remain in the defined state for the duration of the timer

delay. If the input changes state during the delay, the timer is reset.

The sequence detector can also help to identify monitoring

faults. In the sample application shown in Figure 22, the FSEL1

and FSEL2 states first identify which of the VP1, VP2, or VP3

pins has faulted, and then they take appropriate action.

SEQUENCE

STATES

IDLE1

VX1 = 0

IDLE2

MONITOR FAULT

STATES

VP1 = 1

EN3V3

VP1 = 0

10ms

TIMEOUT

STATES

VP2 = 1

EN2V5

(VP1 + VP2) = 0

20ms

VP3 = 1

DIS3V3

VX1 = 1

(VP1 + VP2 + VP3) = 0

FSEL1

(VP1 +

VP2) = 0

PWRGD

DIS2V5

VP2 = 0

VX1 = 1

VX1 = 1

VP3 = 0

FSEL2

VP1 = 0

VP2 = 0

Figure 22. Sample Application Flow Diagram

DIS3V3

0

1

1

DIS2V5

1

0

1

PWRGD

1

1

0

FSEL1

1

1

1

FSEL2

1

1

1

Rev. E | Page 17 of 28

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