ADG1236
TEST CIRCUITS
V
S
D
IDS
VS
Figure 20. Test Circuit 1—On Resistance
IS (OFF)
A
S
VS
ID (OFF)
D
A
VD
Figure 21. Test Circuit 2—Off Resistance
NC
S
ID (ON)
D
A
NC = NO CONNECT
VD
Figure 22. Test Circuit 3—On Leakage
VDD
0.1μF
VSS
0.1μF
VS
VIN
VDD
SB
SA
VSS
D
IN
GND
RL
300Ω
VOUT
CL
35pF
VIN
VIN
VOUT
50%
50%
90%
tON
Figure 23. Test Circuit 4—Switching Times
50%
50%
90%
tOFF
VDD
0.1μF
VSS
0.1μF
VS
VIN
VDD
SB
SA
VSS
D
IN
GND
RL
300Ω
VOUT
CL
35pF
VIN
VOUT 80%
tBBM
Figure 24. Test Circuit 5—Break-Before-Make Time Delay
tBBM
VDD
0.1μF
VSS
0.1μF
VS
VIN
VDD
D
IN
VSS
SB
SA
GND
NC
VOUT
CL
1nF
VIN (NORMALLY
CLOSED SWITCH)
VIN (NORMALLY
OPEN SWITCH)
VOUT
ΔVOUT
ON
QINJ = CL × ΔVOUT
OFF
Figure 25. Test Circuit 6—Charge Injection
Rev. 0 | Page 12 of 16