Data Sheet
TYPICAL APPLICATION CIRCUITS
GND
VTP
50Ω
50Ω
VIN
VP
VN ADCMP580
Q
Q
VTN
LATCH
INPUTS
Figure 16. Zero-Crossing Detector with CML Outputs on the ADCMP580
VTP
VP
VP
VN ADCMP581
Q
VN
Q
VTN
50Ω
50Ω
VTT
LATCH
INPUTS
Figure 17. LVDS to a 50 Ω Back-Terminated (RS) ECL Receiver on the ADCMP581
ADCMP580
HYS
0Ω TO 5kΩ
50Ω
50Ω
VEE
Figure 18. Adding Hysteresis Using the HYS Control on the ADCMP580
VIN
+
ADCMP580
VTH
–
GND
50Ω
50Ω
Q
Q
LATCH
INPUTS
Figure 19. Comparator with −2 to +3 V Input Range on the ADCMP580
ADCMP580/ADCMP581/ADCMP582
VP
ADCMP580
CML
VN
1kΩ
VEE
50Ω
50Ω
Figure 20. Disabling the Latch Feature on the ADCMP580
VP
ADCMP581
VN
750Ω
VTT = –2V VEE
RSECL
50Ω
50Ω
VTT
Figure 21. Disabling the Latch Feature on the ADCMP581
VP
ADCMP582
VN
RSPECL
750Ω
50Ω
50Ω
VCCO
VTT = VCCO – 2V
Figure 22. Disabling the Latch Feature on the ADCMP582
Rev. B | Page 11 of 16