AD9823 查看數據表（PDF） - Analog Devices
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AD9823 Datasheet PDF : 8 Pages
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AD9823
TIMING SPECIFICATIONS
Table 4. TMIN to TMAX, VDD = 3.0 V, fSAMP = 40 MHz, unless otherwise noted.
Parameter (See Figure 3)
Symbol
Sample Clocks
SHP, SHD Clock Period
tCP
SHP Pulse Width
tSHP
SHD Pulse Width
tSHD
CLP Pulse Width1
tCOB
SHP Rising Edge to SHD Rising Edge
tS1
SHD Rising Edge to SHP Rising Edge
tS2
Internal Clock Delay
tID
Recommended Data CLK Timing (for AD9821)
tREC
Min
Typ
Max
Unit
25
5
6.25
5
6.25
4
10
12.0
12.5
12.0
12.5
3.0
4.5
ns
ns
ns
pixels
ns
ns
ns
ns
1 Minimum CLP pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance. Specifications subject to
change without notice.
Rev. 0 | Page 4 of 8
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