AD9637BCPZRL7-80 查看數據表（PDF） - Analog Devices

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AD9637BCPZRL7-80

Octal, 12-Bit, 40/80 MSPS, Serial LVDS, 1.8 V Analog-to-Digital Converter

Analog Devices 

AD9637

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

DC Specifications ......................................................................... 3

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 5

Switching Specifications .............................................................. 6

Timing Specifications .................................................................. 6

Absolute Maximum Ratings............................................................ 8

Thermal Characteristics .............................................................. 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 11

AD9637-80 .................................................................................. 11

AD9637-40 .................................................................................. 14

Equivalent Circuits ......................................................................... 17

Theory of Operation ...................................................................... 18

Analog Input Considerations.................................................... 18

Voltage Reference ....................................................................... 19

Clock Input Considerations ...................................................... 20

Power Dissipation and Power-Down Mode ........................... 22

Digital Outputs and Timing ..................................................... 23

Built-In Output Test Modes .......................................................... 27

Output Test Modes..................................................................... 27

Serial Port Interface (SPI).............................................................. 28

Configuration Using the SPI..................................................... 28

Hardware Interface..................................................................... 29

Configuration Without the SPI ................................................ 29

SPI Accessible Features.............................................................. 29

Memory Map .................................................................................. 30

Reading the Memory Map Register Table............................... 30

Memory Map Register Table..................................................... 31

Memory Map Register Descriptions........................................ 34

Applications Information .............................................................. 36

Design Guidelines ...................................................................... 36

Power and Ground Recommendations ................................... 36

Clock Stability Considerations ................................................. 36

Exposed Pad Thermal Heat Slug Recommendations............ 36

VCM............................................................................................. 36

Reference Decoupling................................................................ 36

SPI Port ........................................................................................ 36

Outline Dimensions ....................................................................... 37

Ordering Guide .......................................................................... 37

REVISION HISTORY

4/13—Rev. 0 to Rev. A

Added Common-Mode Range ....................................................... 3

Changes to AC Specifications Section ........................................... 4

Added Propagation Delay of 1.5 ns Min and 3.1 ns Max; Table 4 .. 6

Added CLK Divider = 8 to Figure 7, Figure 9, Figure 10, and

Figure 11 Captions.......................................................................... 11

Added CLK Divider = 8 to Figure 22, Figure 24, and Figure 25

Captions ........................................................................................... 14

Changes to Figure 36 and Figure 37............................................. 17

Changes to Figure 44...................................................................... 18

Changes to Figure 56...................................................................... 22

Changes to Digital Outputs and Timing Section ....................... 23

Changes to Channel Specific Registers Section.......................... 30

Changes to Register 0x21, Bit 3; Table 17.................................... 33

Changes to Bits[6:4]—Input Clock Phase Adjust Section......... 35

Added Clock Stability Considerations Section........................... 36

Updated Outline Dimensions ....................................................... 37

10/11—Revision 0: Initial Version

Rev. A | Page 2 of 40

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