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AD9515/PCBZ(RevA) 查看數據表（PDF） - Analog Devices

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AD9515/PCBZ
(Rev.:RevA)

1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs

Analog Devices

AD9515/PCBZ Datasheet PDF : 28 Pages

1 2 3 4 5 6 7 8 9 10 Next Last

Data Sheet

Parameter

S0 = 1

Zero Scale Delay Time2

Zero Scale Variation with Temperature

Full Scale Time Delay2

Full Scale Variation with Temperature

Linearity, DNL

Linearity, INL

Min Typ

0.56

0.47

11.4

−5

0.2

Max Unit Test Conditions/Comments

ps/°C

LSB

1 This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature.

2 Incremental delay; does not include propagation delay.

AD9515

CLOCK OUTPUT PHASE NOISE

CLK input slew rate = 1 V/ns or greater.

Table 4.

Parameter

CLK-TO-LVPECL ADDITIVE PHASE NOISE

CLK = 622.08 MHz, OUT = 622.08 MHz

Divide = 1

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

>1 MHz Offset

CLK = 622.08 MHz, OUT = 155.52 MHz

Divide = 4

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

>1 MHz Offset

CLK = 622.08 MHz, OUT = 38.88 MHz

Divide = 16

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

>1 MHz Offset

CLK = 491.52 MHz, OUT = 61.44 MHz

Divide = 8

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

> 1 MHz Offset

Min Typ

Max Unit

Test Conditions/Comments

−125

−132

−140

−148

−153

−154

−128

−140

−148

−155

−161

−135

−145

−158

−165

−166

−131

−142

−153

−160

−165

dBc/Hz

Rev. A | Page 5 of 28

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