AD9287(Rev0) 查看數據表（PDF） - Analog Devices
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AD9287 Datasheet PDF : 52 Pages
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AD9287
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 3.
Parameter1
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS (PDWN, SCLK/DTP)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (SDIO/ODM)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDIO/ODM)
Logic 1 Voltage (IOH = 50 μA)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL OUTPUTS (D+, D−), (ANSI-644)1
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
DIGITAL OUTPUTS (D+, D−),
(Low Power, Reduced Signal Option)1
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
Temp
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Full
Full
Min
250
1.2
1.2
1.2
0
1.79
247
1.125
AD9287-100
Typ
Max
Unit
CMOS/LVDS/LVPECL
1.2
20
1.5
mV p-p
V
kΩ
pF
3.6
V
0.3
V
30
kΩ
0.5
pF
3.6
V
0.3
V
70
kΩ
0.5
pF
DRVDD + 0.3 V
0.3
V
30
kΩ
2
pF
V
0.05
V
LVDS
454
mV
1.375
V
Offset binary
LVDS
Full
150
250
mV
Full
1.10
1.30
V
Offset binary
1 See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.
2 This is specified for LVDS and LVPECL only.
Rev. 0 | Page 5 of 52
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