AD8328ACPZ-REEL 查看數據表（PDF） - Analog Devices
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AD8328ACPZ-REEL Datasheet PDF : 20 Pages
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AD8328
1 TOKO 458 PT-1087 used for above specifications. Typical insertion loss of 0.3 dB @ 10 MHz.
2 Guaranteed by design and characterization to ±4 sigma for TA = 25°C.
3 Measured through a 2:1 transformer.
4 Specification is worst case over all gain codes.
5 Guaranteed by design and characterization to ±3 sigma for TA = 25°C.
6 VIN = 29 dBmV, QPSK modulation, 160 kSPS symbol rate.
LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC)
DATEN, CLK, SDATA, TXEN, SLEEP, VCC = 5 V; full temperature range.
Table 2.
Parameter
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current (VINH = 5 V) CLK, SDATA, DATEN
Logic 0 Current (VINL = 0 V) CLK, SDATA, DATEN
Logic 1 Current (VINH = 5 V) TXEN
Logic 0 Current (VINL = 0 V) TXEN
Logic 1 Current (VINH = 5 V) SLEEP
Logic 0 Current (VINL = 0 V) SLEEP
Min
Typ
Max
Unit
2.1
5.0
V
0
0.8
V
0
20
nA
–600
–100
nA
50
190
μA
−250
−30
μA
50
190
μA
−250
−30
μA
TIMING REQUIREMENTS
Full temperature range, VCC = 5 V, tR = tF = 4 ns, fCLK = 8 MHz, unless otherwise noted.
Table 3.
Parameter
Clock Pulse Width (tWH)
Clock Period (tC)
Setup Time SDATA vs. Clock (tDS)
Setup Time DATEN vs. Clock (tES)
Hold Time SDATA vs. Clock (tDH)
Hold Time DATEN vs. Clock (tEH)
Input Rise and Fall Times, SDATA, DATEN, Clock (tR, tF)
Min
Typ
Max
Unit
16.0
ns
32.0
ns
5.0
ns
15.0
ns
5.0
ns
3.0
ns
10
ns
Rev. A | Page 4 of 20
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