AD8145YCPZ-R2(Rev0) 查看數據表（PDF） - Analog Devices

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AD8145YCPZ-R2
(Rev.:Rev0)

High Speed, Triple Differential Receiver with Comparators

Analog Devices 

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter

Supply Voltage

Power Dissipation

Storage Temperature Range

Operating Temperature Range

Lead Temperature Range (Soldering 10 sec)

Junction Temperature

Rating

12 V

See Figure 2

–65°C to +125°C

–40°C to +105°C

300°C

150°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, θJA is

specified for a device soldered in the circuit board with its

exposed paddle soldered to a pad on the PCB surface, which is

thermally connected to a copper plane.

Table 4. Thermal Resistance

Package Type

θJA

5 mm × 5 mm, 32-Lead LFCSP 47

θJC Unit

8.5 °C/W

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

–40 –20

0

20

40

60

80

100

AMBIENT TEMPERATURE (°C)

Figure 2. Maximum Power Dissipation vs. Temperature for a 4-Layer Board

AD8145

Maximum Power Dissipation

The maximum safe power dissipation in the AD8145 package is

limited by the associated rise in junction temperature (TJ) on

the die. At approximately 150°C, which is the glass transition

temperature, the plastic changes its properties. Even temporarily

exceeding this temperature limit can change the stresses that the

package exerts on the die, permanently shifting the parametric

performance of the AD8145. Exceeding a junction temperature

of 150°C for an extended period of time can result in changes in

the silicon devices, potentially causing failure.

The power dissipated in the package (PD) is the sum of the

quiescent power dissipation and the power dissipated in the

package due to the load drive for all outputs. The quiescent

power is the voltage between the supply pins (VS) times the

quiescent current (IS). The power dissipated due to the load

drive depends upon the particular application. For each output,

the power due to load drive is calculated by multiplying the load

current by the associated voltage drop across the device. The

power dissipated due to all of the loads is equal to the sum of

the power dissipation due to each individual load. RMS voltages

and currents must be used in these calculations.

Airflow increases heat dissipation, effectively reducing θJA. Also,

more metal directly in contact with the package leads from

metal traces, through-holes, ground, and power planes reduces

the θJA. The exposed paddle on the underside of the package

must be soldered to a pad on the PCB surface, which is

thermally connected to a copper plane to achieve the specified θJA.

Figure 2 shows the maximum safe power dissipation in the

package vs. the ambient temperature for the 32-lead LFCSP

(47°C/W) on a JEDEC standard 4-layer board with the

underside paddle soldered to a pad, which is thermally

connected to a PCB plane.

ESD CAUTION

Rev. 0 | Page 7 of 24

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