AD7899BR-1 查看數據表（PDF） - Analog Devices
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AD7899BR-1 Datasheet PDF : 16 Pages
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AD7899
Pin
No.
1
2, 6
3, 4
5
7–13
14
15
16–22
23
24
25
26
27
28
PIN FUNCTION DESCRIPTIONS
Mnemonic
VREF
GND
VINB, VINA
VDD
DB13–DB7
OPGND
VDRIVE
DB6–DB0
BUSY/EOC
RD
CS
CONVST
CLKIN
STBY
Description
Reference Input/Output. This pin is provides access to the internal reference (2.5 V ± 20 mV) and
also allows the internal reference to be overdriven by an external reference source (2.5 V ± 5%).
A 0.1 µF decoupling capacitor should be connected between this pin and GND.
Ground Pin. This pin should be connected to the system’s analog ground plane.
Analog Inputs. See Analog Input Section.
Positive Supply Voltage, 5.0 V ± 5%.
Data Bit 13 is the MSB, followed by Data Bit 12 to Data Bit 7. Three-state outputs.
Output Driver Ground. This is the ground pin of the output drivers for D13 to D0 and BUSY/EOC. It should
be connected to the system’s analog ground plane .
This pin provides the positive supply voltage for the digital inputs and outputs. It is normally tied to VDD
but may also be powered by a 3 V ± 10% supply which allows the inputs and outputs to be interfaced
to 3 V processors and DSPs. VDRIVE should be decoupled with a 0.1 µF capacitor to GND.
Data Bit 6 to Data Bit 0. Three-state Outputs.
BUSY/EOC Output. Digital output pin used to signify that a conversion is in progress or that a conversion
has finished. The function of the BUSY/EOC is determined by the state of CONVST at the end of con-
version. See the Timing and Control Section.
Read Input. Active low logic input which is used in conjunction with CS low to enable the data outputs.
Chip Select Input. Active low logic input. The device is selected when this input is active.
Convert Start Input. Logic Input. A low to high transition on this input puts the track/hold into hold mode
and starts conversion.
Conversion Clock Input. CLKIN is an externally applied clock which allows the user to control the
conversion rate of the AD7899. If the CLKIN input is high on the rising edge of CONVST an externally
applied clock will be used as the conversion clock. If the CLKIN is low on the rising edge of CONVST
the internal laser-trimmed oscillator is used as the conversion clock. Each conversion needs sixteen clock
cycles in order for the conversion to be completed. The externally applied clock should have a duty cycle
no greater than 60/40. The CLKIN pin can be tied to GND if an external clock is not required.
Standby Mode Input. Logic input which is used to put the device into the power save or standby mode.
The STBY input is high for normal operation and low for standby operation.
PIN CONFIGURATION
SOIC/SSOP
VREF 1
28 STBY
GND 2
27 CLKIN
VINB 3
26 CONVST
VINA 4
VDD 5
25 CS
24 RD
GND 6
23 BUSY/EOC
AD7899
DB13 7 TOP VIEW 22 DB0
DB12 8 (Not to Scale) 21 DB1
DB11 9
20 DB2
DB10 10
19 DB3
DB9 11
18 DB4
DB8 12
17 DB5
DB7 13
16 DB6
OPGND 14
15 VDRIVE
–6–
REV. A
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