AD7763 查看數據表（PDF） - Analog Devices
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AD7763 Datasheet PDF : 32 Pages
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Data Sheet
AD7763
TIMING SPECIFICATIONS
AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, TA = 25°C, normal mode, unless otherwise noted.
Table 3.
Parameter
fMCLK
fICLK
t11
t21
t3
t3A 4
t3B4
t45
t4A4, 5
t4B4, 5
t5
t64
t7
t8
t9
t10
t11
t12
t13
t14
t15
Limit at TMIN, TMAX
1
40
500
20
1 × tICLK or 0.5 × tICLK2
1 × tICLK or 0.5 × tICLK2
tSCO 3
2
3
32 × tSCO3
1
2
6.5
5
0.5 × tSCO3
16 × tSCO3
tSCO3
5.5
1 × tSCO3
12
10
12
16 × tSCO3
Unit
MHz min
MHz max
kHz min
MHz max
typ
typ
typ
ns typ
ns typ
typ
ns typ
ns typ
ns max
ns max
ns min
typ
typ
ns max
min
ns min
ns min
ns min
typ
Description
Applied master clock frequency
Internal modulator clock derived from MCLK
SCO high period
SCO low period
DRDY low period
SCO rising edge to DRDY falling edge
SCO rising edge to DRDY rising edge
FSO low period
SCO rising edge to FSO falling edge
SCO falling edge to FSO rising edge
Initial data access time
SCO rising edge to SDO valid
SDO valid after SCO falling edge
DRDY rising edge to SDL falling edge
SDL pulse width
SDO three-state to SCO rising edge
FSI low period
SDI setup time
SDI hold time
FSI setup time
SDL falling edge to SDL falling edge
1 tICLK = 1/fICLK.
2 SCO frequency selected by SCR and CDIV pins.
3 tSCO = t1 + t2.
4 All edges mentioned refer to SCP = 0. Invert SCO edges for SCP = 1.
5 In decimate × 32 mode, this time specification applies only when CDIV = 0 and SCR =1. For all other combinations of CDIV and SCR in decimate × 32 mode, the FSO
signal is constantly logic low.
Rev. B | Page 5 of 32
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