AD7666ACP 查看數據表（PDF） - Analog Devices

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AD7666ACP

16-Bit 500 kSPS PulSAR® Unipolar ADC with Reference

Analog Devices 

MASTER SERIAL INTERFACE

Internal Clock

The AD7666 is configured to generate and provide the serial

data clock SCLK when the EXT/INT pin is held LOW. The

AD7666 also generates a SYNC signal to indicate to the host

when the serial data is valid. The serial clock SCLK and the

SYNC signal can be inverted if desired. Depending on the

RDC/SDIN input, the data can be read after each conversion or

during the following conversion. Figure 39 and Figure 40 show

detailed timing diagrams of these two modes.

AD7666

Usually, because the AD7666 is used with a fast throughput, the

Master Read During Conversion mode is the most recommen-

ded serial mode. In this mode, the serial clock and data toggle at

appropriate instants, minimizing potential feedthrough between

digital activity and critical conversion decisions.

In Read After Conversion mode, it should be noted that unlike

in other modes, the BUSY signal returns LOW after the 16 data

bits are pulsed out and not at the end of the conversion phase,

which results in a longer BUSY width.

CS, RD

t3

CNVST

EXT/INT = 0

RDC/SDIN = 0

INVSCLK = INVSYNC = 0

BUSY

SYNC

SCLK

SDOUT

t28

t30

t29

t25

t14

t18

t19

t20

t21

1

2

3

t15

X

D15

D14

t16

t22

t23

t24

t26

14

15

16

t27

D2

D1

D0

Figure 39. Master Serial Data Timing for Reading (Read after Convert)

CS, RD

CNVST

BUSY

EXT/INT = 0

t1

t3

RDC/SDIN = 1

INVSCLK = INVSYNC = 0

SYNC

SCLK

SDOUT

t17

t14

t19

t20 t21

t15

1

2

3

t18

X

D15

D14

t25

t24

t26

14

15

16

t27

D2

D1

D0

t16

t22

t23

Figure 40. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)

Rev. 0 | Page 23 of 28

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