AD7393AR(RevA) 查看數據表（PDF） - Analog Devices
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AD7393AR Datasheet PDF : 11 Pages
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AD7392/AD7393
ABSOLUTE MAXIMUM RATINGS*
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
VOUT to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . 50 mA
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +2 V
Package Power Dissipation . . . . . . . . . . . . . (TJ max – TA)/θJA
Thermal Resistance θJA
20-Lead Plastic DIP Package (N-20) . . . . . . . . . . . 57°C/W
20-Lead SOIC Package (R-20) . . . . . . . . . . . . . . . . 60°C/W
20-Lead Thin-Shrink Surface Mount (RU-20) . . . 155°C/W
Maximum Junction Temperature (TJ max) . . . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
AD7393AR . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature
N-20 (Soldering, 10 sec) . . . . . . . . . . . . . . . . . . . . . +300°C
R-20 (Vapor Phase, 60 sec) . . . . . . . . . . . . . . . . . . .+215°C
RU-20 (Infrared, 15 sec) . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
1
CS
0
1
DB11–DB0
0
tCS
tDS
tDH
DATA VALID
1
tRS
RS
0
FS
VOUT
ZS
؎0.1% FS
ERROR BAND
tS
tS
Figure 3. Timing Diagram
1 OF 12 LATCHES
OF THE
DAC REGISTER
DBX
CS
TO
INTERNAL
DAC
SWITCHES
RS
Figure 4. Digital Control Logic
PIN CONFIGURATIONS
VDD 1
SHDN 2
CS 3
RS 4
20 VREF
19 VOUT
18 AGND
17 DGND
D0 5
D1 6
D2 7
AD7392 16 D11
TOP VIEW 15 D10
(Not to Scale)
14 D9
D3 8
13 D8
D4 9
12 D7
D5 10
11 D6
VDD 1
SHDN 2
CS 3
RS 4
20 VREF
19 VOUT
18 AGND
17 DGND
NC 5 AD7393 16 D9
NC 6 TOP VIEW 15 D8
(Not to Scale)
D0 7
14 D7
D1 8
13 D6
D2 9
12 D5
D3 10
11 D4
NC = NO CONNECT
PIN DESCRIPTION
# Name Function
1 VDD
Positive Power Supply Input. Specified range
of operation +2.7 V to +5.5 V.
2 SHDN Power Shutdown active low input. DAC regis-
ter contents are saved as long as power stays on
the VDD pin. When SHDN = 0, CS strobes will
write new data into the DAC register.
3 CS
Chip Select latch enable, active low.
4 RS
Resets DAC register to zero condition. Asyn-
chronous active low input.
5, 6 NC
No connect Pins 5 and 6 on the AD7393.
17 DGND Digital Ground.
18 AGND Analog Ground.
19 VOUT
20 VREFIN
DAC Voltage Output.
DAC Reference Input Pin. Establishes DAC
full-scale voltage.
D0–D11 12 parallel input data bits. D11 = MSB Pin 16,
D0 = LSB Pin 5, AD7392.
D0–D9 10 parallel input data bits. D9 = MSB. Pin 16,
D0 = LSB Pin 7, AD7393.
ORDERING GUIDE
Model
Res
Package
(LSB) Temp Description
Package
Option
AD7392AN 12
AD7392AR 12
AD7393AN 10
AD7393AR 10
AD7393ARU 10
XIND
XIND
XIND
AUTO
XIND
20-Lead P-DIP
20-Lead SOIC
20-Lead P-DIP
20-Lead SOIC
TSSOP-20
N-20
R-20
N-20
R-20
RU-20
NOTES
XIND = –40°C to +85°C; AUTO = –40°C to +125°C.
The AD7392 contains 709 transistors. The die size measures 78 mil × 85 mil =
6630 sq. mil.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7392/AD7393 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. A
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