EVAL-AD7264EDZ(RevD) 查看數據表（PDF） - Analog Devices

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EVAL-AD7264EDZ
(Rev.:RevD)

1 MSPS, 14-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators

Analog Devices 

Data Sheet

AD7264

Parameter

Min

POWER REQUIREMENTS

AVCC

4.75

CA_CBVCC, CC_CDVCC

2.7

VDRIVE

2.7

IDD

ADC Normal Mode (Static)

ADC Normal Mode (Dynamic)

Shutdown Mode

Power Dissipation

ADC Normal Mode (Static)

ADC Normal Mode (Dynamic)

Shutdown Mode

Typ

Max

5.25

5.25

5.25

20

31.5

23

33.3

0.5

1

105

165

120

175

2.625 5.25

Unit

V

V

V

mA

mA

μA

mW

mW

µW

Test Conditions/Comments

Digital inputs = 0 V or VDRIVE

AVCC = 5.25 V

fS = 1 MSPS, AVCC = 5.25 V

AVCC = 5.25 V, ADCs and comparators

powered down

1 These specifications were determined without the use of the gain calibration feature.

2 See the Terminology section.

3 Samples are tested during initial release to ensure compliance; they are not subject to production testing.

4 For PGA gain = 1, to utilize the full analog input range (VCM ± VREF/2) of the AD7264, the VCM voltage should be dropped to lie within a range from 1.95 V to 2.05 V.

5 Refers to Pin VREFA or Pin VREFB.

6 This specification includes the IDD for both comparators. The IDD per comparator is the specified value divided by 2.

Rev. D | Page 5 of 29

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