XWM8728EDS/R 查看數據表（PDF） - Wolfson Microelectronics plc
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XWM8728EDS/R Datasheet PDF : 28 Pages
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WM8728
MPU 3-WIRE INTERFACE TIMING
Production Data
Figure 4 Program Register Input Timing - 3-Wire Serial Control Mode
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
Program Register Input Information
SCK rising edge to LATI2S
tSCS
rising edge
SCK pulse cycle time
tSCY
SCK pulse width low
tSCL
SCK pulse width high
tSCH
SDIDEM to SCK set-up time
tDSU
SCK to SDIDEM hold time
LATI2S pulse width low
LATI2S pulse width high
LATI2S rising to SCK rising
CSBIWL to LATI2S set-up time
LATI2S to CSBIWL hold time
tDHO
tCSL
tCSH
tCSS
tCSSU
tCSSH
TEST CONDITIONS
MIN
TYP
MAX
40
80
20
20
20
20
20
20
20
20
20
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
w
PD Rev 4.2 April 2004
10
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