AD7091R(Rev0) 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
生产厂家
AD7091R Datasheet PDF : 20 Pages
| |||
Data Sheet
AD7091R
TIMING SPECIFICATIONS
VDD = 2.75 V to 5.25 V, VDRIVE = 1.65 V to 5.25 V, TA = −40°C to +125°C, unless otherwise noted.1
Table 2.
Parameter
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
tQUIET
Limit at TMIN, TMAX
50
8
7
0.4 tSCLK
3
0.4 tSCLK
15
10
650
6
18
8
8
50
100
50
Unit
MHz max
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns max
ns min
ns min
ms typ
µs max
ns min
Description
Frequency of serial read clock
Delay from the end of a conversion until SDO three-state is disabled
Data access time after SCLK falling edge
SCLK high pulse width
SCLK to data valid hold time
SCLK low pulse width
SCLK falling edge to SDO high impedance
CONVST pulse width
Conversion time
CS low time before the end of a conversion
Delay from CS until SDO three-state is disabled
CS high time before the end of a conversion
Delay from the end of a conversion until CS falling edge
Power-up time with internal reference2
Power-up time with external reference
Time between last SCLK edge and next CONVST pulse
1 Sample tested during initial release to ensure compliance.
2 With a 2.2 µF reference capacitor.
Rev. 0 | Page 5 of 20
Share Link: 