AD5666(RevA) 查看數據表（PDF） - Analog Devices
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AD5666 Datasheet PDF : 28 Pages
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AD5666
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE2
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Zero-Code Error Drift
Full-Scale Error
Gain Error
Gain Temperature Coefficient
Offset Error
DC Power Supply Rejection
Ratio
DC Crosstalk
(External Reference)
DC Crosstalk
(Internal Reference)
OUTPUT CHARACTERISTICS3
Output Voltage Range
Capacitive Load Stability
DC Output Impedance
Short-Circuit Current
Power-Up Time
REFERENCE INPUTS
Reference Input Voltage
Reference Current
Reference Input Range
Reference Input Impedance
REFERENCE OUTPUT
Output Voltage
Reference TC3
Reference Output
Impedance
LOGIC INPUTS3
Input Current
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance
A Grade1
Min Typ Max
16
±32
±1
1
9
±2
−0.2 −1
±1
±2.5
±1 ±9
–80
10
5
10
25
10
0
VDD
2
10
0.5
30
4
VDD
20 30
0
VDD
14.6
2.495
±5
7.5
2.505
±10
±3
0.8
2
3
B Grade1
Min Typ Max
16
±16
±1
1
9
±2
−0.2 −1
±1
±2.5
±1 ±9
–80
10
5
10
25
10
0
VDD
2
10
0.5
30
4
VDD
20 30
0
VDD
14.6
2.495
±5
7.5
2.505
±10
±3
0.8
2
3
Unit
Bits
LSB
LSB
mV
μV/°C
% FSR
% FSR
ppm
mV
dB
μV
μV/mA
μV
μV
μV/mA
V
nF
nF
Ω
mA
μs
V
μA
V
kΩ
V
ppm/°C
kΩ
μA
V
V
pF
Conditions/Comments
See Figure 6
Guaranteed monotonic by design
(see Figure 7)
All 0s loaded to DAC register (see Figure 13)
All 1s loaded to DAC register (see Figure 12)
Of FSR/°C
VDD ± 10%
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
Due to load current change
Due to powering down (per channel)
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
Due to load current change
RL = ∞
RL = 2 kΩ
VDD = 5 V
Coming out of power-down mode VDD = 5 V
VREF = VDD = 5.5 V
Per DAC channel
At ambient
All digital inputs
VDD = 5 V
VDD = 5 V
Rev. A | Page 3 of 28
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