AD5668BRUZ-1REEL7 查看數據表（PDF） - Analog Devices

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AD5668BRUZ-1REEL7

Octal, 12-/14-/16-Bit, SPI Voltage Output denseDAC with 5 ppm/°C, On-Chip Reference

Analog Devices 

Data Sheet

AD5628/AD5648/AD5668

BALL A1

INDICATOR

1

2

3

4

GND SCLK DIN SYNC

A

VOUTB LDAC VDD VOUTA

B

VOUTF VOUTD VOUTE VOUTC

C

VOUTH CLR VREF VOUTG

D

TOP VIEW

(BALL SIDE DOWN)

Not to Scale

Figure 6. 16-Ball WLCSP (CB-16-16)

Table 8. 16-Ball WLCSP Pin Function Descriptions

Pin. No. Mnemonic Description

B2

LDAC

Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows

all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low.

A4

SYNC

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it

powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges

of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge of SYNC acts as an

interrupt and the write sequence is ignored by the device.

B3

VDD

Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a

10 μF capacitor in parallel with a 0.1 μF capacitor to GND.

B4

VOUTA

Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

B1

VOUTB

Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

C4

VOUTC

Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

C2

VOUTD

Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

D3

VREFIN/VREFOUT The AD5628/AD5648/AD5668 have a common pin for reference input and reference output. When using the

internal reference, this is the reference output pin. When using an external reference, this is the reference input

pin. The default for this pin is as a reference input.

D2

CLR

Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored.

When CLR is activated, the input register and the DAC register are updated with the data contained in the CLR

code register—zero, midscale, or full scale. Default setting clears the output to 0 V.

C3

VOUTE

Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.

C1

VOUTF

Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.

D4

VOUTG

Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.

D1

VOUTH

Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.

A1

GND

Ground Reference Point for All Circuitry on the Part.

A3

DIN

Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling edge of the

serial clock input.

A2

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can

be transferred at rates of up to 50 MHz.

Rev. J | Page 11 of 30

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