NXP Semiconductors
74LVT16245B; 74LVTH16245B
3.3 V 16-bit transceiver; 3-state
5. Pinning information
5.1 Pinning
74LVT16245B
74LVTH16245B
1DIR 1
1B0 2
1B1 3
GND 4
1B2 5
1B3 6
VCC 7
1B4 8
1B5 9
GND 10
1B6 11
1B7 12
2B0 13
2B1 14
GND 15
2B2 16
2B3 17
VCC 18
2B4 19
2B5 20
GND 21
2B6 22
2B7 23
2DIR 24
48 1OE
47 1A0
46 1A1
45 GND
44 1A2
43 1A3
42 VCC
41 1A4
40 1A5
39 GND
38 1A6
37 1A7
36 2A0
35 2A1
34 GND
33 2A2
32 2A3
31 VCC
30 2A4
29 2A5
28 GND
27 2A6
26 2A7
25 2OE
001aae471
Fig 3. Pin configuration for SSOP48 and TSSOP48
74LVT16245B
1
2
3
4
5
6
A 1DIR n.c. n.c. n.c. n.c. 1OE
B 1B1 1B0 GND GND 1A0 1A1
C 1B3 1B2 VCC VCC 1A2 1A3
D 1B5 1B4 GND GND 1A4 1A5
E 1B7 1B6
1A6 1A7
F 2B0 2B1
2A1 2A0
G 2B2 2B3 GND GND 2A3 2A2
H 2B4 2B5 VCC VCC 2A5 2A4
J 2B6 2B7 GND GND 2A7 2A6
K 2DIR n.c. n.c. n.c. n.c. 2OE
001aae474
Transparent top view
Fig 4. Pin configuration for VFBGA56
74LVT_LVTH16245B_7
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 07 — 29 March 2010
© NXP B.V. 2010. All rights reserved.
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