Philips Semiconductors
3.3V Octal bus transceiver/register (3-State)
Product specification
74LVT646
DC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
Temp = -40°C to +85°C
MIN
TYP
NO TAG
MAX
UNIT
VIK
Input clamp voltage
VCC = 2.7V; IIK = –18mA
–0.9 –1.2 V
VCC = 2.7 to 3.6V; IOH = –100µA
VCC-0.2 VCC-0.1
VOH High-level output voltage
VCC = 2.7V; IOH = –8mA
2.4
2.5
V
VCC = 3.0V; IOH = –32mA
2.0
2.2
VCC = 2.7V; IOL = 100µA
0.1
0.2
VCC = 2.7V; IOL = 24mA
0.3
0.5
VOL
Low–level output voltage
VCC = 3.0V; IOL = 16mA
0.25
0.4
V
VCC = 3.0V; IOL = 32mA
0.3
0.5
VCC = 3.0V; IOL = 64mA
0.4
0.55
VRST Power-up output low voltage5 VCC = 3.6V; IO = 1mA; VI = GND or VCC
0.13 0.55 V
II
Input leakage current
VCC = 3.6V; VI = VCC or GND
VCC = 0 or 3.6V; VI = 5.5V
VCC = 3.6V; VI = 5.5V
VCC = 3.6V; VI = VCC
Control pins
I/O Data pins4
±0.1
±1
1
10
1
20
µA
0.1
1
VCC = 3.6V; VI = 0
–1
-5
IOFF Output off current
IHOLD Bus Hold current A inputs6
IEX
Current into an output in the
High state when VO > VCC
VCC = 0V; VI or VO = 0 to 4.5V
VCC = 3V; VI = 0.8V
VCC = 3V; VI = 2.0V
VCC = 0V to 3.6V; VCC = 3.6V
VO = 5.5V; VCC = 3.0V
75
–75
±500
1
±100 µA
150
–150
µA
60
125 µA
IPU/PD
Power up/down 3-State output VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or VCC;
current3
OE/OE =Don’t care
15
±100 µA
ICCH
VCC = 3.6V; Outputs High, VI = GND or VCC, IO = 0
0.13 0.19
ICCL Quiescent supply current
VCC = 3.6V; Outputs Low, VI = GND or VCC, IO = 0
3
12 mA
ICCZ
VCC = 3.6V; Outputs Disabled; VI = GND or VCC, IO = 0
0.13 0.19
∆ICC
Additional supply current per
input pin2
VCC = 3V to 3.6V; One input at VCC-0.6V,
Other inputs at VCC or GND
0.1
0.2 mA
NOTES:
1. All typical values are at and Tamb = 25°C.
2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND
3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 3.3V ± 0.3V a
transition time of 100µsec is permitted. This parameter is valid for Tamb = 25°C only.
4. Unused pins at VCC or GND.
5. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
6. This is the bus hold overdrive current required to force the input to the opposite logic state.
1998 Feb 19
6