74LVC126APW 查看數據表（PDF） - Philips Electronics
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74LVC126APW Datasheet PDF : 20 Pages
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Philips Semiconductors
Quad buffer/line driver with 5 Volt
tolerant input/outputs; 3-state
Product specification
74LVC126A
FEATURES
• 5 V tolerant inputs/outputs for interfacing with 5 V logic
• Wide supply voltage range from 1.2 to 3.6 V
• CMOS low power consumption
• Direct interface with TTL levels
• Inputs accept voltages up to 5.5 V
• Complies with JEDEC standard no. 8-1A
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from −40 to +85 °C and −40 to +125 °C.
DESCRIPTION
The 74LVC126A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices.
In 3-state operation, outputs can handle 5 V.
The 74LVC126A consists of four non-inverting buffers/line
drivers with 3-state outputs (nY) which are controlled by
the output enable input (nOE). A LOW at nOE causes the
outputs to assume a high-impedance OFF-state.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
PARAMETER
tPHL/tPLH
CI
CPD
propagation delay nA to nY
input capacitance
power dissipation capacitance per gate
CONDITIONS
CL = 50 pF; VCC = 3.3 V
VCC = 3.3 V;
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
TYPICAL
2.4
4.0
12
UNIT
ns
pF
pF
ORDERING INFORMATION
TYPE NUMBER
74LVC126AD
74LVC126ADB
74LVC126APW
74LVC126ABQ
TEMPERATURE RANGE
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
PINS
14
14
14
14
PACKAGE
PACKAGE MATERIAL
SO14
SSOP14
TSSOP14
DHVQFN14
plastic
plastic
plastic
plastic
CODE
SOT108-1
SOT337-1
SOT402-1
SOT762-1
2003 Feb 28
2
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