74LV165 查看數據表（PDF） - NXP Semiconductors.

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74LV165

8-bit parallel-in/serial-out shift register

NXP Semiconductors. 

Nexperia

74LV165

8-bit parallel-in/serial-out shift register

9,

3/LQSXW

*1'

9,

&(&3LQSXW

*1'

92+

4RU4RXWSXW

92/

90

W:

WUHP

W3+/

90

90

DDD

Fig 8.

Measurement points are given in Table 8.

The changing to output assumes that internal Q6 is opposite state from Q7.

Parallel load (PL) pulse width, parallel load to output (Q7 or Q7) propagation delays, parallel load to clock

(CP) and clock enable (CE) recovery time

9,

'LQSXW

*1'

92+

4RXWSXW

92/

92+

4RXWSXW

92/

90

W3/+

90

W3+/

90

W3+/

W3/+

DDD

Fig 9.

Measurement points are given in Table 8.

The changing to output assumes that internal Q6 is opposite state from Q7.

Data input (Dn) to output (Q7 or Q7) propagation delays when PL is LOW

74LV165

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 9 March 2016

© Nexperia B.V. 2017. All rights reserved

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