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74HC193DB

Presettable synchronous 4-bit binary up/down counter

NXP Semiconductors. 

NXP Semiconductors

74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

MR(1)

PL

D0

D1

D2

D3

CPU(2)

CPD(2)

Q0

Q1

Q2

Q3

TCU

TCD

0

13

CLEAR PRESET

14 15

0

1

2

COUNT UP

1

0

15 14 13

COUNT DOWN

001aag411

(1) Clear overrides load, data and count inputs.

(2) When counting up, the count down clock input (CPD) must be HIGH, when counting down the count up clock input

(CPU) must be HIGH.

Sequence

Clear (reset outputs to zero);

load (preset) to binary thirteen;

count up to fourteen, fifteen, terminal count up, zero, one and two;

count down to one, zero, terminal count down, fifteen, fourteen and thirteen.

Fig 8. Typical clear, load and count sequence

74HC_HCT193

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 24 June 2013

© NXP B.V. 2013. All rights reserved.

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