Philips Semiconductors
2.5V/3.3V 20-bit bus interface latch (3-State)
Product specification
74ALVT16841
FEATURES
• High speed parallel latches
• 5V I/O Compatible
• Live insertion/extraction permitted
• Extra data width for wide address/data paths or buses carrying
parity
• Power-up 3-State
• Power-up reset
• Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per Jedec Std 17
• Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The 74ALVT16841 Bus interface latch is designed to provide extra
data width for wider data/address paths of buses carrying parity. It is
designed for VCC operation at 2.5V or 3.3V with I/O compatibility to
5V.
The 74ALVT16841 consists of two sets of ten D-type latches with
3-State outputs. The flip-flops appear transparent to the data when
Latch Enable (nLE) is High. This allows asynchronous operation, as
the output transition follows the data in transition. On the nLE
High-to-Low transition, the data that meets the setup and hold time
is latched.
Data appears on the bus when the Output Enable (nOE) is Low.
When nOE is High the output is in the High-impedance state.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH
tPHL
CIN
COut
ICCZ
Propagation delay
nDx to nQx
Input capacitance DIR, OE
Output pin capacitance
Total supply current
CONDITIONS
Tamb = 25°C
CL = 50pF
VI = 0V or VCC
VI/O = 0V or VCC
Outputs disabled
TYPICAL
2.5V
3.3V
1.8
1.5
2.1
1.7
3
3
9
9
40
70
UNIT
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
–40°C to +85°C
74ALVT16841 DL
–40°C to +85°C
74ALVT16841 DGG
NORTH AMERICA
AV16841 DL
AV16841 DGG
DWG NUMBER
SOT371-1
SOT364-1
1998 Feb 13
2
853-1868 18961