Logic Diagram
Connection Diagrams
Pin Assignment for TSSOP
Pin Assignment for FBGA
(Top Thru View)
Pin Descriptions
Pin Names
OEn
T/Rn
A0–A15
B0–B15
NC
Description
Output Enable Input (Active LOW)
Transmit/Receive Input
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
No Connect
FBGA Pin Assignments
1
2
3
4
5
6
A
B0
NC T/R1 OE1 NC
A0
B
B2
B1
NC
NC
A1
A2
C
B4
B3 VCCB VCCA A3
A4
D
B6
B5 GND GND A5
A6
E
B8
B7 GND GND A7
A8
F
B10
B9 GND GND A9
A10
G
B12
B11 VCCB VCCA A11
A12
H
B14
B13
NC
NC
A13
A14
J
B15
NC T/R2 OE2
NC
A15
Truth Tables
Inputs
OE1
T/R1
L
L
L
H
H
X
Outputs
Bus B0–B7 Data to Bus A0–A7
Bus A0–A7 Data to Bus B0–B7
HIGH Z State on A0–A7, B0–B7
Inputs
OE2
T/R2
Outputs
L
L
Bus B8–B15 Data to Bus A8–A15
L
H
Bus A8–A15 Data to Bus B8–B15
H
X
HIGH-Z State on A8–A15, B8–B15
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
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