74AHC30 查看數據表（PDF） - Philips Electronics

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74AHC30

8-input NAND gate

Philips Electronics 

Philips Semiconductors

8-input NAND gate

Product specification

74AHC30; 74AHCT30

FEATURES

• ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V

CDM EIA/JESD22-C101 exceeds 1000 V

• Balanced propagation delays

• Inputs accept voltages higher than VCC

• For AHC only: operates with CMOS input levels

• For AHCT only: operates with TTL input levels

• Output capability: standard

• ICC category: SSI

• Specified from −40 to +85 °C and −40 to +125 °C.

DESCRIPTION

The 74AHC/AHCT30 are high-speed Si-gate CMOS

devices and are pin compatible with Low power Schottky

TTL (LSTTL). They are specified in compliance with

JEDEC standard no. 7A.

The 74AHC/AHCT30 provide the 8-input NAND function.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.

SYMBOL

PARAMETER

CONDITIONS

tPHL/tPLH

CI

CO

CPD

propagation delay

A, B, C, D, E, F, G, H to Y

input capacitance

output capacitance

power dissipation capacitance

CL = 15 pF; VCC = 5 V

CL = 50 pF; f = 1 MHz;

notes 1 and 2

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW).

PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

∑ (CL × VCC2 × fo) = sum of outputs;

CL = output load capacitance in pF;

VCC = supply voltage in Volts.

2. The condition is VI = GND to VCC.

TYPICAL

AHC

3.6

AHCT

3.3

3.0

3.0

4.0

4.0

10

12

UNIT

ns

pF

pF

pF

1999 Nov 30

2

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