74AHC164 查看數據表（PDF） - Philips Electronics

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74AHC164

8-bit serial-in/parallel-out shift register

Philips Electronics 

Philips Semiconductors

8-bit serial-in/parallel-out shift register

Product specification

74AHC164; 74AHCT164

FEATURES

• ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V

CDM EIA/JESD22-C101 exceeds 1000 V

• Balanced propagation delays

• All inputs have Schmitt-trigger actions

• Inputs accept voltages higher than VCC

• For AHC only: operates with CMOS input levels

• For AHCT only: operates with TTL input levels

• Specified from −40 to +85 °C and from −40 to +125 °C.

DESCRIPTION

The 74AHC/AHCT164 shift registers are high-speed

silicon-gate CMOS devices and are pin compatible with

Low power Schottky TTL (LSTTL). They are specified in

compliance with JEDEC standard No. 7A.

The 74AHC/AHCT164 input signals are 8-bit serial

through one of two inputs (Dsa or Dsb); either input can be

used as an active HIGH enable for data entry through the

other input. Both inputs must be connected together or an

unused input must be tied HIGH.

Data shifts one place to the right on each LOW-to-HIGH

transition of the clock (CP) input and enters into Q0, which

is a logical AND of the two data inputs (Dsa, Dsb) that

existed one set-up time prior to the rising clock edge.

A LOW level on the master reset (MR) input overrides all

other inputs and clears the register asynchronously,

forcing all outputs LOW.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.

SYMBOL

PARAMETER

CONDITIONS

tPHL/tPLH

CI

fmax

CPD

propagation delay

CP to Qn

MR to Qn

input capacitance

maximum clock frequency

power dissipation capacitance

CL = 15 pF; VCC = 5 V

VI = VCC or GND

CL = 15 pF; VCC = 5 V

CL = 50 pF; f = 1 MHz; notes 1 and 2

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW).

PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

∑ (CL × VCC2 × fo) = sum of outputs;

CL = output load capacitance in pF;

VCC = supply voltage in Volts.

2. The condition is VI = GND to VCC.

TYPICAL

UNIT

AHC AHCT

4.5 3.4 ns

4.0 3.5 ns

3

3

pF

175 175 MHz

48

51

pF

2000 Aug 15

2

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