48SD6404RPFH 查看數據表（PDF） - MAXWELL TECHNOLOGIES

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48SD6404RPFH

256 Mb SDRAM 16-Meg X 4-Bit X 4-Banks

MAXWELL TECHNOLOGIES 

256Mb (16-Meg X 4-Bit X 4-Banks) SDRAM

48SD6404

DQM Truth Table

COMMAND

SYMBOL

CKE = N-1

CKE = N

DQM

Nibble(DQ0 to DQ3) write enable/output

MASK

H

x

L

enable

Nibble(DQ0 to DQ3) write enable/output

ENBL

H

x

H

enable

Note: H: VIH L: VIL x VIH or VIL

Write: IDID is Needed

Read: IDOD is Needed

The SDRAM can mask input/output data by means of DQM.

During reading, the output buffer is set to Low-Z by setting DQM to Low, enabling data output. On the other

hand, when DQM is set High, the output buffer becomes High-Z, disabling data output.

During writing, data is written by setting DQM to Low. When DQM is set to High, the previous data is held (

the new data is not written). Desired data can be masked during burst read or burst write by setting DQM.

For more details, refer to the DQM control section of the SDRAM operating instructions.

01.11.05 Rev 2

All data sheets are subject to change without notice 10

©2005 Maxwell Technologies

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