2SK3113 查看數據表（PDF） - NEC => Renesas Technology

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2SK3113

SWITCHING N-CHANNEL POWER MOS FET

NEC => Renesas Technology 

2SK3113

ELECTRICAL CHARACTERISTICS (TA = 25°C)

CHARACTERISTICS

SYMBOL

TEST CONDITIONS

Zero Gate Voltage Drain Current

IDSS

VDS = 600 V, VGS = 0 V

Gate Leakage Current

IGSS

VGS = ±30 V, VDS = 0 V

Gate Cut-off Voltage

VGS(off) VDS = 10 V, ID = 1 mA

Forward Transfer Admittance

| yfs | VDS = 10 V, ID = 1.0 A

Drain to Source On-state Resistance

RDS(on) VGS = 10 V, ID = 1.0 A

Input Capacitance

Ciss

VDS = 10 V

Output Capacitance

Coss

VGS = 0 V

Reverse Transfer Capacitance

Crss

f = 1 MHz

Turn-on Delay Time

td(on)

VDD = 150 V, ID = 1.0 A

Rise Time

tr

VGS = 10 V

Turn-off Delay Time

td(off)

RG = 10 Ω, RL = 10 Ω

Fall Time

tf

Total Gate Charge

QG

VDD = 450 V

Gate to Source Charge

QGS

VGS = 10 V

Gate to Drain Charge

QGD ID = 2.0 A

Body Diode Forward Voltage

VF(S-D) IF = 2.0 A, VGS = 0 V

Reverse Recovery Time

Reverse Recovery Charge

trr

IF = 2.0 A, VGS = 0 V

Qrr

di/dt = 50 A/µs

MIN. TYP. MAX. UNIT

100 µA

±10 µA

2.5

3.5 V

0.5

S

3.3 4.4 Ω

290

pF

60

pF

5

pF

7

ns

2

ns

22

ns

9

ns

9

nC

2.4

nC

2

nC

0.9

V

0.9

µs

2.0

µC

TEST CIRCUIT 1 AVALANCHE CAPABILITY

D.U.T.

RG = 25 Ω

L

PG.

50 Ω

VDD

VGS = 20 → 0 V

ID

VDD

IAS BVDSS

VDS

Starting Tch

TEST CIRCUIT 2 SWITCHING TIME

D.U.T.

RG

PG.

VGS

0

τ

τ = 1 µs

Duty Cycle ≤ 1%

RL

VDD

VGS

VGS

Wave Form

0 10%

VGS

90%

ID

90%

ID

Wave Form

0 10%

td(on)

ID

tr td(off)

90%

10%

tf

ton

toff

TEST CIRCUIT 3 GATE CHARGE

D.U.T.

IG = 2 mA

RL

PG.

50 Ω

VDD

2

Data Sheet D13336EJ3V0DS

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