AD7684BRMZ 查看數據表（PDF） - Analog Devices

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AD7684BRMZ

16-Bit, 100 kSPS PulSAR, Differential ADC in MSOP

Analog Devices 

AD7684

APPLICATION INFORMATION

+IN

REF

GND

MSB

SWITCHES CONTROL

LSB SW+

32,768C 16,384C

4C

2C

C

C

32,768C 16,384C

4C

2C

C

C

COMP

CONTROL

LOGIC

BUSY

OUTPUT CODE

MSB

LSB SW–

CNV

–IN

Figure 20. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7684 is a low power, single-supply, 16-bit ADC using a

successive approximation architecture. It is capable of converting

100,000 samples per second (100 kSPS) and powers down

between conversions. When operating at 10 kSPS, for example,

it consumes typically 150 μW with a 2.7 V supply, ideal for

battery-powered applications.

into a balanced condition. After the completion of this process,

the part returns to the acquisition phase and the control logic

generates the ADC output code.

TRANSFER FUNCTIONS

The ideal transfer function for the AD7684 is shown in

Figure 21 and Table 8.

The AD7684 provides the user with an on-chip, track-and-hold

and does not exhibit any pipeline delay or latency, making it

ideal for multiple, multiplexed channel applications.

The AD7684 is specified from 2.7 V to 5.5 V. It is housed in an

8-lead MSOP.

011...111

011...110

011...101

CONVERTER OPERATION

The AD7684 is a successive approximation ADC based on a

charge redistribution DAC. Figure 20 shows the simplified

schematic of the ADC. The capacitive DAC consists of two

identical arrays of 16 binary-weighted capacitors, which are

connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the

input of the comparator are connected to GND via SW+ and

SW−. All independent switches are connected to the analog

inputs. Therefore, the capacitor arrays are used as sampling

capacitors and acquire the analog signal on the +IN and −IN

inputs. When the acquisition phase is complete and the CS

input goes low, a conversion phase is initiated. When the

conversion phase begins, SW+ and SW− are opened first. The

two capacitor arrays are then disconnected from the inputs and

connected to the GND input. Therefore, the differential voltage

between the inputs, +IN and −IN, captured at the end of the

acquisition phase is applied to the comparator inputs, causing

the comparator to become unbalanced. By switching each

element of the capacitor array between GND and REF, the

comparator input varies by binary-weighted voltage steps

(VREF/2, VREF/4...VREF/65,536). The control logic toggles these

switches, starting with the MSB, to bring the comparator back

100...010

100...001

100...000

–FSR

–FSR + 1 LSB

–FSR + 0.5 LSB

+FSR – 1 LSB

+FSR – 1.5 LSB

ANALOG INPUT

Figure 21. ADC Ideal Transfer Function

Table 8. Output Codes and Ideal Input Voltages

Description

Analog Input

VREF = 5 V

Digital Output Code Hex

FSR − 1 LSB

+4.999847 V 7FFF1

Midscale + 1 LSB +152.6 μV

0001

Midscale

0V

0000

Midscale – 1 LSB −152.6 μV

FFFF

−FSR + 1 LSB

−4.999847 V 8001

−FSR

−5 V

80002

1 This is also the code for an overranged analog input (V+IN − V−IN above

VREF − VGND).

2 This is also the code for an underranged analog input (V+IN − V−IN below

−VREF + VGND).

Rev. A | Page 12 of 16

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