S70WS512N00BFWAA3 查看數據表（PDF） - Spansion Inc.

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S70WS512N00BFWAA3

Same-Die Stacked Multi-Chip Product (MCP) 512 Megabit (32M x 16 bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst-mode Flash Memory

Spansion Inc. 

Advance Information

Figures

Figure 8.1 Synchronous/Asynchronous State Diagram...........................................................................................23

Figure 8.2 Synchronous Read ............................................................................................................................26

Figure 8.3 Single Word Program.........................................................................................................................32

Figure 8.4 Write Buffer Programming Operation ...................................................................................................36

Figure 8.5 Sector Erase Operation ......................................................................................................................38

Figure 8.6 Write Operation Status Flowchart ........................................................................................................45

Figure 9.1 Advanced Sector Protection/Unprotection .............................................................................................51

Figure 9.2 PPB Program/Erase Algorithm .............................................................................................................54

Figure 9.3 Lock Register Program Algorithm.........................................................................................................57

Figure 12.1 Maximum Negative Overshoot Waveform .............................................................................................64

Figure 12.2 Maximum Positive Overshoot Waveform ...............................................................................................64

Figure 12.3 Test Setup .......................................................................................................................................65

Figure 12.4 Input Waveforms and Measurement Levels ...........................................................................................65

Figure 12.5 VCC Power-up Diagram ......................................................................................................................66

Figure 12.6 CLK Characterization .........................................................................................................................68

Figure 12.7 CLK Synchronous Burst Mode Read......................................................................................................69

Figure 12.8 8-word Linear Burst with Wrap Around.................................................................................................70

Figure 12.9 8-word Linear Burst without Wrap Around ............................................................................................70

Figure 12.10 Linear Burst with RDY Set One Cycle Before Data ..................................................................................71

Figure 12.11 Asynchronous Mode Read...................................................................................................................72

Figure 12.12 Reset Timings...................................................................................................................................72

Figure 12.13 Chip/Sector Erase Operation Timings ...................................................................................................74

Figure 12.14 Asynchronous Program Operation Timings ............................................................................................75

Figure 12.15 Synchronous Program Operation Timings .............................................................................................76

Figure 12.16 Accelerated Unlock Bypass Programming Timing ...................................................................................76

Figure 12.17 Data# Polling Timings (During Embedded Algorithm) .............................................................................77

Figure 12.18 Toggle Bit Timings (During Embedded Algorithm) ..................................................................................77

Figure 12.19 Synchronous Data Polling Timings/Toggle Bit Timings ............................................................................78

Figure 12.20 DQ2 vs. DQ6 ....................................................................................................................................78

Figure 12.21 Latency with Boundary Crossing when Frequency > 66 MHz....................................................................79

Figure 12.22 Latency with Boundary Crossing into Program/Erase Bank ......................................................................80

Figure 12.23 Example of Wait State Insertion ..........................................................................................................81

Figure 12.24 Back-to-Back Read/Write Cycle Timings ...............................................................................................82

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S70WS512N00 Based MCPs

S70WS512N00_00_A0 March 14, 2005

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