NBC12429AFA 查看數據表（PDF） - ON Semiconductor
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NBC12429AFA Datasheet PDF : 21 Pages
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NBC12429, NBC12429A
Table 8. AC CHARACTERISTICS (VCC = 3.125 V to 5.25 V; TA = 0°C to 70°C (NBC12429), TA = --40°C to 85°C (NBC12429A))
(Note 6)
Symbol
Characteristic
Condition
Min
Max Unit
ts
Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
ns
20
20
th
Hold Time
S_DATA to S_CLOCK
M, N to P_LOAD
20
ns
20
tpwMIN
Minimum Pulse Width
S_LOAD
P_LOAD
50
ns
50
DCO
Output Duty Cycle
47.5
52.5
%
tr, tf
Output Rise/Fall
FOUT 20%--80%
175
425
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
6. FOUT/FOUT outputs are terminated through a 50 Ω resistor to VCC -- 2.0 V.
7. 10 MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at higher frequencies when used
as a test clock in TEST_MODE 6.
FUNCTIONAL DESCRIPTION
The internal oscillator uses the external quartz crystal as
the basis of its frequency reference. The output of the
reference oscillator is divided by 16 before being sent to the
phase detector. With a 16 MHz crystal, this provides a
reference frequency of 1 MHz. Although this data sheet
illustrates functionality only for a 16 MHz crystal, Table 9,
any crystal in the 10 MHz -- 20 MHz range can be used,
Table 11.
The VCO within the PLL operates over a range of 200 to
400 MHz. Its output is scaled by a divider that is configured
by either the serial or parallel interfaces. The output of this
loop divider is also applied to the phase detector.
The phase detector and the loop filter force the VCO
output frequency to be M times the reference frequency by
adjusting the VCO control voltage. Note that for some
values of M (either too high or too low), the PLL will not
achieve loop lock.
The output of the VCO is also passed through an output
divider before being sent to the PECL output driver. This
output divider (N divider) is configured through either the
serial or the parallel interfaces and can provide one of four
division ratios (1, 2, 4, or 8). This divider extends the
performance of the part while providing a 50% duty cycle.
The output driver is driven differentially from the output
divider and is capable of driving a pair of transmission lines
terminated into 50 Ω to VCC -- 2.0 V. The positive reference
for the output driver and the internal logic is separated from
the power supply for the PLL to minimize noise induced
jitter.
The configuration logic has two sections: serial and
parallel. The parallel interface uses the values at the M[8:0]
and N[1:0] inputs to configure the internal counters.
Normally upon system reset, the P_LOAD input is held
LOW until sometime after power becomes valid. On the
LOW--to--HIGH transition of P_LOAD, the parallel inputs
are captured. The parallel interface has priority over the
serial interface. Internal pullup resistors are provided on the
M[8:0] and N[1:0] inputs to reduce component count in the
application of the chip.
The serial interface logic is implemented with a fourteen
bit shift register scheme. The register shifts once per rising
edge of the S_CLOCK input. The serial input S_DATA must
meet setup and hold timing as specified in the AC
Characteristics section of this document. With P_LOAD
held high, the configuration latches will capture the value of
the shift register on the HIGH--to--LOW edge of the
S_LOAD input. See the programming section for more
information.
The TEST output reflects various internal node values and
is controlled by the T[2:0] bits in the serial data stream. See
the programming section for more information.
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