MCP41100-IP 查看數據表（PDF） - Microchip Technology

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MCP41100-IP

Single/Dual Digital Potentiometer with SPI™ Interface

Microchip Technology 

2.1 Parametric Test Circuits

V+ = VDD

A 1LSB = V+/256

V+

W

B

DUT

+

-

VMEAS*

*Assume infinite input impedance

FIGURE 2-25:

Potentiometer Divider Non-

Linearity Error Test Circuit (DNL, INL).

No Connection

A

BW

DUT

IW

+

- VMEAS*

*Assume infinite input impedance

FIGURE 2-26:

Resistor Position Non-

Linearity Error Test Circuit (Rheostat operation

DNL, INL).

DUT

A

W

B

ISW

Rsw = 0.1V

Isw

Code = 00h

+

0.1V

-

VSS = 0 to VDD

FIGURE 2-27:

Circuit.

Wiper Resistance Test

MCP41XXX/42XXX

VA

VDD A

V+

BW

DUT

+

-

VMEAS*

V+ = VDD ± 10%

PSRR (dB) = 20LOG (∆∆VVMDDEAS)

PSS (%/%) = ∆VDD

∆VMEAS

*Assume infinite input impedance

FIGURE 2-28:

Power Supply Sensitivity

Test Circuit (PSS, PSRR).

VIN ~

OFFSET

GND

A

W

DUT

B

2.5V DC

+5V

+

-

VOUT

FIGURE 2-29:

Circuit.

Gain vs. Frequency Test

~ VIN

A DUT B

+5V

2.5V DC

Offset

-

VOUT

+ MCP601

FIGURE 2-30:

Capacitance Test Circuit.

 2003 Microchip Technology Inc.

DS11195C-page 11

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