EP2C50AU208I7ES 查看數據表（PDF） - Altera Corporation
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EP2C50AU208I7ES Datasheet PDF : 168 Pages
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Cyclone II Architecture
The direct link interconnect allows an LAB, M4K memory block, or
embedded multiplier block to drive into the local interconnect of its left
and right neighbors. Only one side of a PLL block interfaces with direct
link and row interconnects. The direct link interconnect provides fast
communication between adjacent LABs and/or blocks without using
row interconnect resources.
The R4 interconnects span four LABs, three LABs and one M4K memory
block, or three LABs and one embedded multiplier to the right or left of a
source LAB. These resources are used for fast row connections in a four-
LAB region. Every LAB has its own set of R4 interconnects to drive either
left or right. Figure 2–8 shows R4 interconnect connections from an LAB.
R4 interconnects can drive and be driven by LABs, M4K memory blocks,
embedded multipliers, PLLs, and row IOEs. For LAB interfacing, a
primary LAB or LAB neighbor (see Figure 2–8) can drive a given R4
interconnect. For R4 interconnects that drive to the right, the primary
LAB and right neighbor can drive on to the interconnect. For R4
interconnects that drive to the left, the primary LAB and its left neighbor
can drive on to the interconnect. R4 interconnects can drive other R4
interconnects to extend the range of LABs they can drive. Additionally,
R4 interconnects can drive R24 interconnects, C4, and C16 interconnects
for connections from one row to another.
Figure 2–8. R4 Interconnect Connections
R4 Interconnect
Driving Left
Adjacent LAB can
Drive onto Another
LAB's R4 Interconnect
C4 Column Interconnects (1)
R4 Interconnect
Driving Right
LAB
Neighbor
Primary
LAB (2)
Notes to Figure 2–8:
(1) C4 interconnects can drive R4 interconnects.
(2) This pattern is repeated for every LAB in the LAB row.
LAB
Neighbor
Altera Corporation
February 2007
2–11
Cyclone II Device Handbook, Volume 1
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