EP2C50AQ324I6N 查看數據表（PDF） - Altera Corporation
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EP2C50AQ324I6N Datasheet PDF : 168 Pages
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Altera Corporation
February 2008
DC Characteristics and Timing Specifications
Table 5–56. Maximum DCD for SDR Output on Column I/O Notes (1), (2)
(Part 2 of 2)
Column I/O Output Standard
2.5-V
1.8-V
1.5-V
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential SSTL-18 Class II
Differential HSTL-18 Class I
Differential HSTL-18 Class II
Differential HSTL-15 Class I
Differential HSTL-15 Class II
LVDS
Simple RSDS
Mini-LVDS
C6
C7
C8
Unit
140
140
155
ps
115
115
165
ps
745
745
770
ps
60
60
75
ps
60
60
80
ps
60
130
130
ps
60
135
135
ps
60
115
115
ps
75
75
100
ps
150
150
150
ps
135
135
155
ps
60
60
75
ps
60
60
80
ps
60
130
130
ps
60
135
135
ps
60
115
115
ps
75
75
100
ps
150
150
150
ps
135
135
155
ps
60
60
60
ps
60
70
70
ps
60
60
60
ps
Notes to Table 5–56:
(1) The DCD specification is characterized using the maximum drive strength
available for each I/O standard.
(2) Numbers are applicable for commercial, industrial, and automotive devices.
Table 5–57. Maximum for DDIO Output on Row Pins with PLL in the Clock
Path Notes (1), (2) (Part 1 of 2)
Row Pins with PLL in the Clock Path C6
C7
C8 Unit
LVCMOS
270
310
310
ps
LVTTL
285
305
335
ps
2.5-V
180
180
220
ps
1.8-V
165
175
205
ps
5–71
Cyclone II Device Handbook, Volume 1
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