3.7 Power-down Mode
The ATF16V8C includes an optional pin controlled power-down feature. Device Pin 4 can be configured as the
power-down pin. When this feature is enabled and the power-down pin is high, total current consumption drops
to less than 100μA. In the power-down mode, all output data and internal logic states are latched and held. All
registered and combinatorial output data remains valid. Any outputs that were in a high-Z state at the onset of
power-down will remain at high-Z. During power-down, all input signals except the power-down pin are blocked.
The input and I/O pin-keeper circuits remain active to insure that pins do not float to indeterminate levels. This
helps to further reduce system power.
Selection of the power-down option is specified in the ATF16V8C logic design file. The logic compiler will
include this option selection in the otherwise standard 16V8 JEDEC fuse file. When the power-down feature is
not specified in the design file, Pin 4 is available as a logic input, and there is no power-down pin. This allows
the ATF16V8C to be programmed using any existing standard 16V8 fuse file.
Note: Some programmers list the JEDEC-compatible 16V8C (No PD used) separately from the non-JEDEC
compatible 16V8CEXT (EXT for extended features).
3.7.1 Power-down AC Characteristics
Table 3-5. Power-down AC Characteristics(1)(2)(3)
Symbol
tIVDH
tGVDH
tCVDH
tDHIX
tDHGX
tDHCX
tDLIV
tDLGV
tDLCV
tDLOV
Parameter
Valid Input Before PD High
Valid OE Before PD High
Valid Clock Before PD High
Input Don’t Care After PD High
OE Don’t Care After PD High
Clock Don’t Care After PD High
PD Low to Valid Input
PD Low to Valid OE
PD Low to Valid Clock
PD Low to Valid Output
Notes: 1. Output data is latched and held.
2. HI-Z outputs remain HI-Z.
3. Clock and input transitions are ignored.
-5
Min
Max
5.0
0
0
5.0
5.0
5.0
5.0
15.0
15.0
20.0
-7
Min
Max
7.5
0
0
7.5
7.5
7.5
7.5
20.0
20.0
25.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ATF16V8C [DATASHEET]
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Atmel-0425I-PLD-ATF16V8C-Datasheet_032014