MT46V64M8(2001) 查看數據表（PDF） - Micron Technology
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MT46V64M8 Datasheet PDF : 68 Pages
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ADVANCE
512Mb: x4, x8, x16
DDR SDRAM
CK#
CK
CKE
COMMAND5
x4: A0-A9, A11
x8: A0-A9
x16: A0-A8
x4: A12
x8: A11, A12
x16: A9, A11, A12
A10
T0
tIS tIH
tIS tIH
NOP6
BA0, BA1
T1
tCK
WRITE – DM OPERATION
T2
T3
T4 T4n T5 T5n T6
tCH tCL
ACT
tIS tIH
RA
RA
NOP6
RA
tIS tIH
Bank x
tRCD
tRAS
WRITE2
Col n
NOP6
tIS tIH
3
Bank x
tDQSS(NOM)
NOP6
NOP6
T7
T8
NOP6
PRE
tWR
ALL BANKS
ONE BANK
Bank x4
tRP
DQS
tWPRES tWPRE
tDQSL tDQSH tWPST
DQ1
DI
b
DM
tDS
tDH
NOTE: 1. DI n = data-out from column n; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T8.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these times.
7. tDSH is applicable during tDQSS(MIN) and is referenced from CK T4 or T5.
8. tDSS is applicable during tDQSS(MAX) and is referenced from CK T5 or T6.
TRANSITIONING DATA
DON’T CARE
TIMING PARAMETERS
SYMBOL
tCH
tCL
tCK (2.5)
tCK (2)
tDH
tDS
tDQSH
tDQSL
tDQSS
tDSS
-75Z
MIN MAX
0.45 0.55
0.45 0.55
7.5
13
7.5
13
0.5
0.5
0.35
0.35
0.75 1.25
0.2
-75
MIN MAX
0.45 0.55
0.45 0.55
7.5
13
10
13
0.5
0.5
0.35
0.35
0.75 1.25
0.2
-8
MIN MAX
0.45 0.55
0.45 0.55
8
13
10
13
0.6
0.6
0.35
0.35
0.75 1.25
0.2
UNITS
tCK
tCK
ns
ns
ns
ns
tCK
tCK
tCK
tCK
SYMBOL
tDSH
tIH
tIS
tRAS
tRCD
tRP
tWPRE
tWPRES
tWPST
tWR
-75Z
MIN MAX
0.2
1
1
40 120,000
20
20
0.25
0
0.4
0.6
15
-75
MIN MAX
0.2
1
1
40 120,000
20
20
0.25
0
0.4
0.6
15
-8
MIN MAX UNITS
0.2
tCK
1.1
ns
1.1
ns
40 120,000 ns
20
ns
20
ns
0.25
tCK
0
ns
0.4
0.6
tCK
15
ns
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65 – Rev. B; Pub 4/01
67
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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