MT46V64M8(2001) 查看數據表（PDF） - Micron Technology

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MT46V64M8
(Rev.:2001)

DOUBLE DATA RATE (DDR) SDRAM

Micron Technology 

ADVANCE

512Mb: x4, x8, x16

DDR SDRAM

CK#

CK1

CKE1

COMMAND4

ADDR

DQS

DQ

DM

T0

tCH

tIS tIH

tIS tIH

NOP

tRP2

SELF REFRESH MODE

T1

tCL

tIS

Ta01

((

))

Ta1

Tb0

((

))

((

((

))

tCK

))

tIS

((

))

((

((

))

))

((

))

AR

((

))

((

))

((

))

((

))

NOP

((

VALID

))

tIS tIH

((

))

VALID

((

))

((

))

((

))

((

))

((

))

((

))

((

))

Enter Self Refresh Mode

((

))

((

))

((

))

((

))

((

))

((

))

tXSNR/

tXSRD3

Exit Self Refresh Mode

DON’T CARE

NOTE: 1. Clock must be stable before exiting self refresh mode. That is, the clock must be cycling within

specifications by Ta0.

2. Device must be in the all banks idle state prior to entering self refresh mode.

3. tXSNR is required before any non-READ command can be applied, and tXSRD (200 cycles of CK)

is required before a READ command can be applied.

4. AR = AUTO REFRESH command.

TIMING PARAMETERS

SYMBOL

tCH

tCL

tCK (2.5)

tCK (2)

tIH

-75Z

MIN MAX

0.45 0.55

0.45 0.55

7.5

13

7.5

13

1

-75

MIN MAX

0.45 0.55

0.45 0.55

7.5

13

10

13

1

-8

MIN MAX

0.45 0.55

0.45 0.55

8

13

10

13

1.1

UNITS

tCK

tCK

ns

ns

ns

SYMBOL

tIS

tRP

tXSNR

tXSRD

-75Z

MIN MAX

1

20

75

200

-75

MIN MAX

1

20

75

200

-8

MIN MAX

1.1

20

80

200

UNITS

ns

ns

ns

tCK

512Mb: x4, x8, x16 DDR SDRAM

512Mx4x8x16DDR_B.p65 – Rev. B; Pub 4/01

62

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc.

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